This application relates generally to read-only memories (ROM's) and more particularly to high-speed readout circuits for semiconductor ROM's.
In the past, semiconductor ROM's have been developed, involving X-Y matrices of field-effect transistors, particularly of the type known as MOSFETs, IGFETs, or by similar names. One typical example, is described in Heeren-Winston U.S. Pat. No. 3,618,050. This type of ROM involves an array of memory cells, each programmed during manufacture to have an operative field-effect transistor present or absent in the cell, in accordance with binary data permanently or semipermanently stored in the memory. X-Y accessing circuitry is provided to "select" the individual cells, when readout is required. This turns ON the cell transistor if an operative transistor was formed or is "present" in the selected cell, but does not turn on a cell "transistor" where either no transistor was formed or a potential transistor there formed is "inoperative" at the cell voltage employed. There are many ways to program the cells with a pattern of operative and inoperative transistors, such as growing thin (operative) or thick (inoperative) gate oxide, implanation of the gate channels so as to increase the threshold voltage of the inoperative devices, etc. The main feature of these devices is that, in one case, as for a stored binary 1, the cell transistor turns ON to present a low cell impedance, and for the other case, as binary 0, the "transistor" cannot turn ON, thus offering a high cell impedance.
To interrogate this type of ROM, and provide a binary output indicative of the stored data, various forms of readout devices have been proposed, two examples of which are disclosed in the Heeren-Winston patent. In general, such readout circuits, by one means or another, apply a voltage to the ROM cell, and then sense a difference in voltage at some point in the circuit based on whether the cell transistor is ON or OFF.